This invention relates, in general, to semiconductor processing and more particularly, to methods for forming semiconductor devices having features with sub-photolithographic dimensions.
Semiconductor devices such as insulated gate field effect transistor (IGFET) devices are becoming increasingly important in low voltage applications. As IGFET devices are scaled to smaller and smaller dimensions, manufacturers must refine transistor designs to maintain optimum device performance. Typically, in IGFET devices having channel lengths in the sub-micron range, manufacturers must carefully fabricate drain regions to avoid performance degradation problems such as hot carrier injection, drain leakage, punch-through, and the like.
Semiconductor manufacturers correct many device performance problems by forming a lightly-doped-drain (LDD) region. The LDD region acts to lower the electric field in the channel region near the drain region. This reduced electric field improves threshold voltage stability by reducing hot carrier injection into the gate oxide layer overlying the channel region. In another approach, manufacturers place a higher doped region in the channel region between the source and drain region and extending from the surface down into the bulk semiconductor material. This higher doped region is of the same conductivity type as the channel region and functions to reduce punch-through.
With the ever increasing demand for higher performance devices, cost effective and flexible methods and structures are needed that allow manufacturers to incorporate performance enhancing features such as those set forth above. It would be advantageous for such structures and methods to support mixed-mode (integrated analog/digital) circuit designs as well as low and high power applications.